1. Field of the Invention
The present invention relates to an image processing system, and more particularly, to an image processing apparatus and a method for implementing picture-in-picture (PIP) with frame rate conversion.
2. Description of the Related Art
In a conventional television (TV), one channel is displayed on a display device. However, a plurality of channels can be displayed on the display device of a TV using a feature called picture-in-picture (PIP). PIP is an image processing method for simultaneously displaying another channel on part of the display device. In prior systems, in order to display PIP, two frame memories for storing asynchronously input image data have been used. Since the size of an image processing apparatus for displaying the PIP is increased by frame memories, such systems can be too large.
In a case where frame rates of input signals are different from that of the display device, a frame rate conversion device is used to adjust the frame rates of the input signals. A conventional frame rate conversion device prevents data from being compromised by synchronizing a clock used as a frame buffer clock with the frequency of each of the input signals using a phase locked loop (PLL). However, in case of using a PLL, the size of a circuit is increased, and a method for operating a frame buffer becomes complicated. Thus, this method is not effective.
Also, for the above-mentioned PIP and frame rate conversion, there are the following problems. For example, assuming that there are two input signals which are asynchronous data, when two input signals are displayed on one display device, the two input signals must be synchronized with each other. Further, in a case where there are limitations in that the display device can not perform a multi-sync function for generating various synchronized signals owing to physical and technical characteristics, a function for simultaneously converting the two input signals to an output frame rate of the display device must be provided. For example, in the case of a liquid crystal device (LCD) monitor, the output frame rate of a display signal in a SXGA level (1280×1024) monitor is physically restricted to 75 KHz or less. Also, the output frame rate in a UXGA level (1600×1200) monitor is restricted to 60 Hz or less. That is, in a case where input signals above the output frame rate are displayed on the display device, the frame rates of the input signals must be reduced. Also, in a case where the frame rates of the two input signals are different, and there is one display device, the frame rates of the two input signals must be independently converted to the output frame rate of the display device. However, in a case where PIP and frame rate conversion are simultaneously performed, a process of synchronizing the two input signals is complicated. During the process, data may be damaged, and the size of a system may be increased by an increase in frame memories.